1. Field of the Invention
The present invention relates to non-volatile memory, and more particularly, to a non-volatile memory that utilizes extra devices to accelerate transient state transitions, and disables extra load units to maintain the sensitivity of operating margins when reading data.
2. Description of the Prior Art
The growth of the so-called information age has led to the storage of mass quantities of information in digital form. Memory storage devices are thus an important topic of research and develop. Flash memory has become prevalent, allowing the access of data at speeds comparable to those of other forms of electronic memory, while storing digital data in a non-volatile manner without requiring any moving parts. Flash memory has thus become one of the most important types of non-volatile storage devices.
Please refer to FIG. 1, which is a circuit diagram of a prior art flash memory 10. The flash memory 10 is biased by DC current Vdd, and has a plurality of memory units 11A and 11B, two on-load isolating units 12A and 12B, a sensor unit SA1, two p-type MOS transistors Ta1 and Ta3 for load units, and a p-type MOS Ta7 for reference units. In memory units 11A and 11B, MOS transistors Ma1 and Ma2 have floating gates to store data. The gates of MOS transistors Ma1, Ma2, TA1 and TA2 are controlled by the controlling voltage Vma1, Vma2, Vd1 and Vd2 respectively to determine whether the MOS is on or off. The MOS transistor TA1 of the memory unit 11A is also electrically connected to one end of the MOS transistor Ma1; the other end serves as a data end, and is electrically connected with on-load isolating at the node Na5. Similarly, an end of MOS transistor TA2 of the memory 11B is electrically connected with the node Na5, and serves as a data end of the memory unit 11B. On-load isolating units 12A and 12B utilize inverters Iva1, Iva2 and p-type MOS transistors Ta5, Ta6, respectively. The p-type MOS transistors serve as a loading unit, connecting to provide negative feedback, of which the source electrode is connected to the node Na1 with the load unit 12A, and the drain electrode is grounded. The source electrode of the MOS transistor Ta3, serving as a third end, connects with the on-load isolating unit 12B at the node Na3, and its drain electrode is grounded. The sensor unit SA1 is a differential sensing amplifier, comprising a first comparing end N1a and a second comparing end N2a, which are connected respectively to the nodes Na1 and Na3; the sensor unit SA1 compares the first comparing end N1a to the second comparing end N2a, and then generate a data signal Vrp1. The MOS transistor Ta7 with a floating gate electrode serves as a reference unit, of which its gate electrode is controlled by the controlling-voltage Vca; one of the other two electrodes is connected to the power Vdd, and the other is connected to the node Na6 with the on-load isolating unit 12B.
The principle of operation for storing data into flash memory is to store each bit to one of the memory units that contains transistors with floating gates. Programming a bit into a memory unit, represented by a binary xe2x80x9c0xe2x80x9d or a binary xe2x80x9c1xe2x80x9d is performed by injecting differing amounts of electric charge. The floating-gate electrode is injected with a different amount of electric charge, which changes the threshold voltage. Even when under the same condition of voltage bias, the different amount of electric charge in the floating-gate results in a different conductance of the MOS transistor, and thus different amounts of data current. Accordingly, it is possible to read out the data stored in the floating-gates of all the memory units. As shown in the FIG. 1, when the memory 10 is to read the binary data stored in the memory unit 11A, the memory 10 controls the controlling-voltage Vma1 to bias and turn on the MOS transistor Ma1 from the gate electrode, and the MOS transistor Ma1 then generates a data current If1. The memory 10 also turns on the MOS transistor TA1 by a high-voltage level Vd1 , so that the data current If1 can flow through the MOS transistor TA1 via the node Na5. Of course, the MOS transistor TA2 of the memory unit 11B is turned off by the controlling-voltage Vd2, which prevents the memory 11B from outputting data current If1 to the node Na5, and thus prevents interfere when reading the data from the memory unit 11A. The on-load insolating unit 12A transmits data current If1 to the node Na1, and injects the current If1 into the MOS transistor Ta1, which is the load unit. With the MOS transistor Ta1 current-biased by this data current If1, the MOS transistor Ta1 establishes a corresponding voltage at the node Na1. When the MOS transistor Ta1 is turned on, the controlling-voltage Vca turns on the MOS transistor Ta7, which also serves as a reference unit, making the MOS transistor Ta7 generate a reference current Ir1, and injecting the current Ir1 into the MOS transistor Ta3. Serving as the load unit, after the MOS transistor Ta3 is biased with this reference current Ir1, the MOS transistor Ta3 generates a corresponding voltage at the node Na3. The sensor unit SA1 compares the voltage at Na1 with the voltage at Na3 through the first comparing end N1a and the second comparing end N2a, and generate a corresponding data signal Vrp1, which reads out the data in the memory unit 11A.
The process of reading data is further illustrated in FIG. 2. Please refer to FIG. 2 and FIG. 3. FIG. 2 is a graph of voltage versus time at first comparing end N1a and the second comparing end N2a when the memory 10 is in process of reading data; the X-axis represents time, and the Y-axis represents the voltage; the curves V(N1a)H and V (N1a)L represent voltage at the first comparing end N1a varying with time, whereas the curve V(N2a) represents the voltage at the second comparing end N2a. Before the timing point ta0, the memory 10 has not yet read the data, and the first and the second comparing ends, N1a and N2a, are charged to high-voltage levels. When the time reaches ta0, the MOS transistors Ma1 and Ta7 generate current, and pull down the voltages of the first comparing end Na1 and the second comparing end Na2. As mentioned above, differing amounts of electric charge stored in the floating gate of the MOS transistor Ma1 in the memory unit 11A results in a different data current If1. When the data current If1 is greater (indicating a lower threshold voltage), the voltage of the first comparing end N1a will have the shape of V(N1a)H, and eventually falls to a higher steady-state voltage VaH; on the other hand, when the data current If2 is smaller, the voltage of the first comparing end N1a will follow curve V(N1a)L, and eventually falls to a lower steady-state voltage VaL. Similarly, the voltage of the second comparing end N2a falls to a steady-state voltage VaR. During the interval between ta0 and ta2, the inverters Iva1 and Iva2 in the on-load isolating units 12A and 12B respectively and adequately bias the MOS transistors Ta5 and Ta6, which lightens the load-effect occurring at the nodes Na1 and Na3 to accelerate the speed at which a steady-state is reached. When the voltages of the two comparing-ends N1a, N2a have reached their respective steady-state voltages, the sensor-unit SA1 determines what data is stored in the memory 11A by detecting the voltage difference between the two comparing ends N1a, n2a. When the voltage of the first comparing end N1a is greater than that of the second comparing end N2a, the electric charge stored in the MOS transistor Ma1 corresponds to a greater data current. The sensor unit SA1 thus decides if the data stored in the memory unit 11A is a binary xe2x80x9c0xe2x80x9d or a binary xe2x80x9c1xe2x80x9d, and accordingly generates a data signal Vrp1.
It""s common to utilize many memory units in an ordinary flash memory, and connect them to the node Na1 through relatively long metal paths. A large capacitance is consequently formed at the node Na1. Decreasing the voltage of the node Na1 to a steady state merely by way of the data current of a memory unit is quite slow. One drawback of the prior art memory 10 is that the process of reading data is easily affected by transient states, or discharging. As shown in FIG. 2, if the sensor unit SA1 incorrectly compares the voltages at the timing-point ta1, regardless of the data current flowing out of the memory unit 11A is great or small, the sensor unit SA1 will erroneously decide that data is stored in the memory unit 11A, since the voltage of the first comparing end N1a is definitely greater than that of the second comparing end N2a.
Please refer to FIG. 3, which is circuit diagram of a prior art memory 20. For the sake of convenience, item numbers marked in FIG. 3 that are the same as those in the FIG. 1 correspond to devices or nodes having the same functionality. The most obvious difference between the memory 20 and the memory 10 is that the memory 20 utilizes an additional equalizing unit 24. Between the first comparing end N1a and the second comparing end N2a of the memory 20 there is a p-type MOS transistor Tta, an n-type MOS transistor Ttb and an inverter Ivb3. The p-type MOS transistor Tta and the n-type MOS transistor Ttb form a transmission gate, where Veq0 controls the transmission gate with the inverter Ivb3. When the transmission gate is on, the nodes Na1 and Na3 are shorted, otherwise, they are opened.
Please refer to FIG. 4A, which is a graph of voltage versus time between the first comparing end N1a and the second comparing end N2a when the memory 20 is reading data. The X-axis of FIG. 4A is time, and the Y-axis is voltage. The curves V (N1a)L and V(N1a)H show how differing data currents result in different voltages at the first comparing end N1a. The curve V(N2b) illustrates the voltage of the second comparing end N2a. Continuing with the example depicted in FIG. 2, it is also assumed that the memory unit 11A of the memory 20 provides a data current If1. Differing from the memory unit 10, however, is that at the timing point ta0, when the memory 20 controls the memory unit 11A to generate the data current If1 and the MOS transistor Ta7 to generate the data current Ir1, the memory 20 also controls the voltage Veq0 to turn on the transmission gate in the equalizing unit 24 to short the nodes Na1 and Na3. Therefore, the voltages of the first and the second comparing ends N1a and N2a are equal, and their voltages changing at the same rate. As shown in FIG. 2, the curves V(N1b)H, V(N1b)L and V(N2b) overlap between the timing points ta0 and tb1. When the timing point tb1 is reached, the controlling voltage Veq0 changes to turn off the transmission gate, and the nodes Na1 and Na3 are no longer shorted through the equalizing unit 24; their reach their respective steady state values. At the time point tb2, the sensor unit SA1 determines the data stored in the memory unit 11A by the voltage difference between the first and the second comparing end N1a and N2a. In short, the memory 20 causes the voltages of the first and the second comparing ends N1a and N2a to be the same by controlling the equalizing unit 24. This prevents the memory unit 20 from incorrectly determining the data during the transient states.
The sensor unit SA1 of memory 20 determines the data stored in the memory unit 11A according to the steady-state-voltages of VaH, VaL and the reference voltage VaR (please refer to FIG. 2 and FIG. 4A). As the differences between these voltages is greater, the SA1 is able to determine and read the data more clearly, and the margin for reading the data is increased as well. The steady-state-voltages VaH and VaL are affected by the following factors: inconsistencies in the semiconductor manufacturing process that makes memory units that are not perfectly identical, noise interference when a read operation is in process, and changes to electrical characteristics because of repeated programming and erasing. If these factor are taken into consideration in advance to increase the operating margin by enlarging the voltage difference between VaH, VaL and VaR, then even when the above factors occur and result in voltage-drifting between VaH and VaL during operation of the memory, the memory is still able to correctly read the data. Since the steady-state-voltages VaH and VaL are established by the data current injecting into the MOS transistor Ta1 (as shown in FIG. 1 and FIG. 3), it is possible to change the characteristics of the MOS transistor TA1 when designing the memory so as to enlarge the voltage difference between VaH and VaL. Generally speaking, if the MOS transistor Ta1 has a smaller aspect ratio (W/L ratio) under the condition of a fixed data current, then the voltage difference between VaH and VaL will be larger. Please refer to FIG. 4B, which is a graph of current versus voltage between the currents of source and drain electrodes and the voltage across the MOS transistor Ta1. If MOS transistor Ta1 has a smaller aspect ratio, its current-voltage curve is as shown by IV1; if MOS transistor Ta1 has a larger aspect ratio, its current-voltage curvature is as shown in IV2. As mentioned above, the supplied current will be different if the data stored in the memory unit is different. The two currents If1 (H) and If1 (L) shown in FIG. 4B illustrate that the memory unit can provide two current levels, and when they are injected into the MOS transistor Ta1, they establish two levels of steady-state-voltages VaH and VaL. As shown in the curve IV1, if the aspect ratio of the MOS transistor Ta1 is smaller, the voltage difference DV1 between the two corresponding steady-state-voltages is larger, as well as the operating margin. On the other hand, as the curve IV2 illustrates, when the aspect ratio of MOS transistor Ta1 is lower, the operating margin DV2 is narrower.
However, it is known in the prior art that decreasing the aspect ratio of the MOS transistor Ta1 also decreases the current-driving ability the MOS transistor. The period of transient states is thus lengthened. Consequently, the period from when the memory unit begins to supply data current and pulls down the voltage of the first comparing end, to the voltage reaching steady state and thus able to be read data, is increased. This decreases the efficiency data accessing. The prior art memory units 10 and 20 are all undermined by their inability to give consideration to both the operating margins and the reading speed.
It is therefore a primary objective of the claimed invention to provide a memory using a two-stage sensing amplifier with an additional load unit to increase the operating margin while maintain a good reading speed, enabling the memory in the claimed invention to read data both quickly and correctly.
In the prior art, to read data in the memory unit, it is required to first establish a voltage by injecting the data current generated from the memory unit into the load unit, and then the sensor unit determines the data condition according to the voltages. In the claimed invention, an enabled and a disabled load unit are added.
During the transient state of reading data from the memory unit, the load unit is enabled to enhance the current-driving ability and decrease the period of the transient state. When the transient state is finished, the load unit is disabled and a smaller aspect ratio load unit is instead used for establishing a final steady-state-voltage to achieve a better operating margin for the claimed invention.